1. Field of the Invention
The present invention generally relates to field effect transistors (FETs) and, more particularly, to double gate FETs configured as finFETs.
2. Description of the Prior Art
Field effect transistors have become the device of choice for fabrication of integrated digital logic circuits operating at all but the highest of clock rates. FETs can be fabricated at extremely small sizes consistent with extremely small minimum feature size regimes. However, some electrical characteristics of FETs may be degraded as FET designs are scaled to such extremely small sizes or operating margins may be reduced due to requirements of electrical breakdown, reduced voltages for thermal management and the like. For example, switching threshold voltages may not be sufficiently uniform to allow reliable operations at current and foreseeable clock rates unless some control therefor is provided. One such control technique is to employ substrate voltage control or a second gate for the FETs in order to more closely control conduction channel conditions. Unfortunately, a second gate is difficult to provide in a common planar FET design having, for example, a conduction channel in a substrate and a gate on the surface thereof. Thus, in order to more easily provide a second gate, so-called finFET designs having the conduction channel parallel to the substrate but oriented orthogonal thereto have been proposed and fabricated in order to provide access to both sides of the conduction channel.
However, finFET designs generally have less doping than semiconductor on insulator (SOI) and bulk devices. This lower doping tends to compromise control of the switching threshold of finFETs. Further, since finFETs are double gate devices, allowing the back gate to be used to adjust the switching threshold, Vt, the back gate also increases capacitance which tends to degrade finFET performance. Moreover, as with SOI and bulk devices when scaled to small sizes, finFETs also exhibit short channel effects (SCE).
It is known that a so-called halo implant can be used to improve short channel effects but such structures, in a finFET, degrades carrier mobility in the channel. Similarly, a super-steep retrograded well can reduce SCE but is very difficult to form the well for planar MOSFET designs.